The INTCON Register
The INTCON register is a readable and writable register which contains the various enable bits for all interrupt sources. The meaning of INTCON might be (though this is only me thinking) INTurrpt CONtrol register. I have serached the net for the source of this acronym with no avail; if you find it please e-mail me. Anyway, interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
This register is used to configure the interrupt control logic circuitry. Bits 0 to 6 are used to configure the interrupt enable/disable statuses and the interrupt flags for the four interrupt sources. No interrupt to the CPU will result unless the GIE bit is set. The GIE bit is the bit INTCON<7> and when set, enables all un-masked interrupts.
|
||||||||||||||||||||||||||||||||||||||||||||||||